PROBLEM TO BE SOLVED: To realize the function clock generating circuit in which a wiring area, a cell area and power consumption are reduced and design of timing is facilitated. ;SOLUTION: An input terminal D of a through-latch circuit LTC11 is connected to an input line of an enable signal EN, an inverted clock input terminal G is connected to an input line of a clock signal CK and one input terminal of a NAND gate NAND11 connects to an output terminal Q of the through-latch circuit LTC11, the other input terminal is connected to an input terminal of the clock signal CK and the output terminal is connected to an input terminal of an inverter INV11. Then the enable signal EN is sampled in the through-latch circuit LTC11 at a rising point of time of the clock signal CK and a logic gate LGT consisting of the NAND gate NAND11 and the inverter INV11 passes or blocks a clock pulse just after sampling depending on the sampled enable signal EN.;COPYRIGHT: (C)1997,JPO
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