Static type random access memory device equipped with variable load circuits for digit line pairs

摘要

A static type random access memory device supplies current from a load circuit (120) to a selected digit line pair (D0/ CD0) in a write-in phase of operation, and the load circuit comprises a first pair of charging transistors (Qp25/ Qp28) coupled between a positive power voltage line (Vdd) and the selected digit line pair in a read-out phase, and a second pair of charging transistor (Qp26/ Qp27) also coupled between the positive power voltage line and the selected digit line pair and responsive to differential voltage indicative of a write-in data bit for selectively coupling one of the digit lines with the positive power voltage line so that the impedance of the load circuit is appropriately adjustable between the read-out phase and the write-in phase.