Automatic detection and enabling/disabling apparatus for computer memory system parity bits

摘要

An automatic memory parity detection and enabling/disabling apparatus for a computer system is disclosed. The computer system comprises a central processing unit, a memory subsystem, a memory controller logic, a memory parity checking logic comprising a plurality of parity bits, and a flagging signal setting logic for selecting the enabling or disabling of the computer system parity checking scheme. The automatic apparatus comprises of multiple-input AND gate and two flip-flops. The multiple inputs of the AND gate are each fetched by one parity bit of the memory parity checking logic, each parity bit is pulled up to the high state signal level of the computer system through a respective resistor. The output of the AND gate is connected to the data input of the first one of the two flip-flops, and the data output of the first flip-flop is connected to the clock input of the second one of the two flip-flops. The data input of the second flip-flop is fetched by flagging signal, the clock input of the first flip-flop is connected to a memory access status signal generated by the memory controller logic, and the preset inputs of the first and second flip-flops are connected together and fetched by a reset signal generated by the computer system.