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High-Voltage CMOS transistors on a standard CMOS wafer
High-Voltage CMOS transistors on a standard CMOS wafer
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机译:标准CMOS晶圆上的高压CMOS晶体管
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摘要
A low-voltage 0.8-micron CMOS process is modified by implanting arsenic or phosphorus during epitaxy in a p-type substrate starting material to increase the depth of selected n-well areas for the purpose of producing high-voltage transistors on the same substrate in the same CMOS process. Implanting boron in a p-field extension area in a manner which minimizes the dopant in the adjacent field oxide achieves a similar result. That is, breakdown and punch-through voltages are increased. Together, these make CMOS transistors which operate at a higher voltage range than either innovation alone.
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