SELF-ALIGNED DIFFUSED SOURCE VERTICAL TRANSISTORS WITH DEEP TRENCH CAPACITORS IN A 4F-SQUARE MEMORY CELL ARRAY

摘要

A densely packed array of vertical semiconductor devices,having pillars (230) and deep trench capacitors (578), andmethods of making thereof are disclosed. The pillars act astransistor channels, formed between upper and lower dopedregions. The lower doped regions are self-aligned located belowthe pillars. The array has columns of bitlines (220) and rowsof wordlines (225). The lower doped regions of all the cellsare isolated from each other without increasing cell size andallowing a minimum area of approximately 4F2 to be maintained.The array may have an open bitline, a folded, or an open/foldedarchitecture with dual wordlines. The lower regions may beinitially implanted. Alternatively, the lower regions may bediffused below the pillars after forming thereof. In this case,the lower region diffusion may be controlled to form floatingpillars isolated from the underlying substrate, or to maintaincontact between the pillars and the substrate.Figure 8