PHASE LOCKED LOOP ERROR SUPPRESSION CIRCUIT AND METHOD

摘要

An error suppressing circuit (301) and method therefor for a phase locked loop(PLL) (300). According to one embodiment of the present invention, a transientcondition, for example, a bandwidth switch, in the PLL (300) is detected. ThePLL (300) is opened for a period of time (509) responsive to detecting thetransient condition. The phase of a reference frequency signal (115) and thephase of an output frequency signal (116 or 117) are synchronized after alapse of the period of time (509). The PLL (300) is closed responsive to thephase of the reference frequency signal (115) and the phase of the outputfrequency signal (116 or 117) being synchronized. The present inventionadvantageously reduces the length of time it takes for the PLL (300) tocorrect for the phase and frequency error generated by the transientcondition, and is capable of operating with various types of PLLs.