Dynamic D-flip-flop circuit for high-speed pre-scalar

摘要

A dynamic D-flip-flop circuit for high speed pre-scalar is disclosed. The NC ² MOS stage receives an input signal to output a first output signal, and the ray latch stage receives a first output signal from the NC ² MOS stage to output a second output signal, and the inverter latches the ray latch stage. The second output signal is received from the inverter and outputs the output signal. According to the above configuration, a dynamic D-flip-flop as a single clock signal based on a CMOS process by designing a dynamic D-flip-flop for high-speed prescales by reducing the number of transistors by a ray logic logic technique; DFF) can be driven.