A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE

摘要

The present invention relates to a synchronous semiconductor memory device, in order to minimize power consumption, the first global control signal (PCSL_ENG) and decoders are used to cause the decoders to be enabled only when there is an input of a decoded address signal. The first and second output control signals PCSL_EN and PCSL_PRE respectively generated in response to the second global control signal PCSL_PREG for enabling the enable state are provided to the corresponding decoders, thereby reducing power consumption as much as possible. In this way, the effect of suppressing the occurrence of noise is obtained.