Vertical metal insulator semiconductor field effect transistor (MISFET)

摘要

A base region (3) of second conductivity is formed in a substrate (1) of first conductivity, to form a drain region. A gate electrode (6) is formed by a gate insulation film (5) in a groove (4) in the base region, around which is formed a source region (7) of first conductivity. The base is be deeper than the groove, under which is formed a semiconductor region of first conductivity and higher doping concentration than the semiconductor substrate. An Independent claim is given for a method for manufacturing a vertical MISFET.