A stacked cmos sram cell with polysilicon - load transistors

摘要

A CMOS SRAM memory cell, and a method of making the same, is disclosed. The disclosed cell is configured as cross-coupled CMOS inverters, with the n-channel pull-down transistors in bulk, and with the p-channel load devices being accumulation mode p-channel transistors in a thin polysilicon film. The cross-coupling connection is made by way of an intermediate layer, which may include polysilicon at its top surface for performance enhancement, each of which makes contact to the drain region of an n-channel transistor, and to the opposite gate electrode, via a buried contact. The intermediate layer also serves as the gate for the thin-film p-channel transistor, which has its channel region overlying the intermediate layer. The p-channel transistors may be formed so as to overlie part of the n-channel transistor in its inverter, thus reducing active chip area required for implementation of the memory cell.