Generation of reference clock frequencies from varying input clock sources

摘要

A plurality of different frequency dividers 311-317 are coupled to an input clock signal 302, and the divided clock signal which is closest in frequency to the desired output reference frequency is selected by multiplexer 320 as the output clock signal 322. The selection is performed in dependence on input frequency data 304 derived from a storage device such as an EEPROM associated with the input frequency source. The division ratio of one divider 317 may be less than unity. A second reference frequency output 324 may be selected. The output clock signals may be used in a local area network interface circuit, and the input clock may be obtained from the host computer or from the network.