Method for forming a deep submicron MOSFET device using a silicidation process

摘要

A process for fabricating a deep submicron MOSFET device has been developed, featuring a local threshold voltage adjust region in a semiconductor substrate, with the threshold voltage adjust region self aligned to an overlying polysilicon gate structure. The process consists of forming a narrow hole opening in a dielectric layer, followed by an ion implantation procedure used to place the threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. A polysilicon deposition, followed by a metal deposition and anneal procedure, converts the unwanted polysilicon to a metal silicide layer, while leaving unconverted polysilicon in the narrow hole opening. Selective removal of the metal silicide layer results in a narrow polysilicon gate structure, in the narrow hole opening, self aligned to the threshold voltage adjust region.