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Vijay A semiconductor package and its manufacturing method

机译:维杰半导体封装及其制造方法

摘要

FIELD OF THE INVENTION The present invention relates to an improved busy semiconductor package and a method for manufacturing the stacked busy semiconductor package.;The semiconductor package for achieving the object of the present invention comprises a semiconductor chip (91) attached to the central recess (53) of the lower substrate (51); A wire 93 connecting one end of a wiring 59 on an upper surface of the lower substrate 51 to the semiconductor chip 91; An encapsulation member (97) surrounding the recess, the wire and the upper surface of the semiconductor chip (91); A lower through hole 55 having an upper portion wider than a lower portion at an outer side of the recess of the lower substrate 51; An upper substrate 71 having a conductive ball 95 mounted on the lower through hole 55 and an upper through hole 75 formed at a portion corresponding to the conductive ball 95 with an upper portion narrower than the lower portion is provided on the lower portion. It is adhered on the substrate 51.;The BG semiconductor package according to the present invention can be stacked up and down, thereby increasing the packaging mounting density while maintaining the advantages of the BG package.
机译:改进的忙碌半导体封装及其制造方法技术领域本发明涉及一种改进的忙碌半导体封装及其制造方法,其用于实现本发明的目的的半导体封装包括附接到中央凹部(200)的半导体芯片(91)。下基板(51)的53);布线93将下基板51的上表面上的布线59的一端连接至半导体芯片91;包围凹部,导线和半导体芯片(91)的上表面的密封构件(97);下部通孔55的下部比下部基板51的凹部的外侧的上部宽。在下部上设置有上基板71,该上基板71具有安装在下部通孔55上的导电球95和形成在与导电球95相对应的部分处的上部通孔75,该上部通孔75的上部比下部窄。它粘附在衬底51上。根据本发明的BG半导体封装可以上下堆叠,从而在保持BG封装优点的同时提高了封装安装密度。

著录项

  • 公开/公告号KR19990086915A

    专利类型

  • 公开/公告日1999-12-15

    原文格式PDF

  • 申请/专利权人 김영환;

    申请/专利号KR19980020097

  • 发明设计人 오성호;

    申请日1998-05-30

  • 分类号H01L23/50;

  • 国家 KR

  • 入库时间 2022-08-22 01:46:26

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