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Method of achieving narrow V.sub.T distribution after erase in flash EEPROM

机译:在闪存EEPROM中擦除后实现窄VTT分布的方法

摘要

There is provided a method of correcting overerased memory cells in a flash EEPROM memory cell after erase so as to produce a narrow threshold voltage distribution width. A ground potential is applied to all of the sources and substrates of the cells in the array of memory cells. First positive pulse voltages are simultaneously applied to each word line in a first timed sequence on a word line by word line basis. A second positive pulse voltage is simultaneously applied to each bit line in a second timed sequence in a bit line by bit line basis when the first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied.
机译:提供了一种在擦除之后校正闪存EEPROM存储单元中被过擦除的存储单元以产生窄的阈值电压分布宽度的方法。接地电势被施加到存储单元阵列中的单元的所有源极和衬底。在每个字线的基础上,以第一定时序列将第一正脉冲电压同时施加到每个字线。当第一正脉冲电压被施加到第一字线时,第二正脉冲电压同时以逐位线的第二定时序列被同时施加到每个位线,然后对于每个随后的字线重复该第二正脉冲电压,直到a最后一个字线被应用。

著录项

  • 公开/公告号US6023426A

    专利类型

  • 公开/公告日2000-02-08

    原文格式PDF

  • 申请/专利权人 EON SILICON DEVICES INC.;

    申请/专利号US19980036971

  • 发明设计人 JAMES C. YU;YUAN TANG;CHIEN-SHENG SU;

    申请日1998-03-09

  • 分类号G11C16/04;

  • 国家 US

  • 入库时间 2022-08-22 01:37:53

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