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Dynamically configurable variable frequency and duty cycle clock and signal generation

机译:可动态配置的可变频率和占空比时钟以及信号生成

摘要

A variable clock generator includes a clock multiplier that generates from a reference clock at least two clock signals which are out of phase with each other and a clock divider which receives a plurality of divider patterns and which receives at least two clock signals from the clock multiplier. The clock divider generates an output clock based on the divider patterns and the clock signals. In a particular embodiment, the clock divider includes a plurality of loadable linear feedback shift registers each having an output. An EXCLUSIVE OR gate that is responsive to the outputs of the linear feedback shift registers then EXCLUSIVE ORs the outputs of the linear feedback shift registers to produce the output clock. Preferably, the size of the linear feedback shift registers corresponds to the size of the divider patterns.
机译:可变时钟发生器包括:时钟倍频器,其从参考时钟生成彼此异相的至少两个时钟信号;以及时钟分频器,其接收多个分频器模式,并且从时钟倍频器接收至少两个时钟信号。 。时钟分频器根据分频器模式和时钟信号生成输出时钟。在特定实施例中,时钟分频器包括多个可加载线性反馈移位寄存器,每个均具有输出。响应线性反馈移位寄存器的输出的异或门,然后将线性反馈移位寄存器的输出进行异或,以产生输出时钟。优选地,线性反馈移位寄存器的大小对应于除法器图案的大小。

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