First the single-phase domino time loan logic circuit which and possesses the clock in last stage, possesses latch in last stage

摘要

(57) Abstract Self timing reset (752) and, the self end pulse clock precharge circuit (730) in 2nd staging which possesses the pulse clock input terminal (712) and the pulse clock input terminal in 1st staging and, receiving easiness of influence of the clock jitter to which the domino logic circuit constitution which includes with the full keeper (734 and 736) in 2nd staging, has time loan function, in high frequency designing is decreased. With one execution form, appraisal of first domino stage (718) of block and both of the self end precharge of last domino stage (746) of block, are started by the startup edge of the pulse clock (702). With the circuit constitution with this invention, it can provide the period when it is almost equal to 3 invertor delays in order to turn off the input to succeeding domino logical stage although the first domino logical stage which therefore is while each blocking is appraised it can obtain sufficient time.