- SINGLE-PHASE DOMINO TIME BORROWING LOGIC WITH CLOCKS AT FIRST AND LAST STAGES AND LATCH AT LAST STAGE

摘要

Pool of removing pulse clock pre-charge circuit, and a second stage-Self-time reset 752, the first stage 712, a pulse clock input terminal, a pulse clock input terminal addition of the second stage (730) having self-of- keeper (734 736) domino logic circuit configurations, including decreases sensitivity to clock jitter in the high-frequency design, and provides a lease time capability. In an embodiment, the first self-domino stage 718 final domino stage 746 with the evaluation blocks in the block - removing the pre-charge is initiated by the rising edge of the clock pulse (702). In the circuit configuration according to the invention, there is provided approximately the same time period and the three inverter delay to turn off the inputs to the next of a domino logic stage, and thus a sufficient time to evaluate the first domino logic stage in each block to provide.