Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage

摘要

A domino logic circuit configuration including self-timed resets (752), a pulsed clock input terminal in a first stage (712), a self-terminating pulsed clock precharge circuit in a second stage (730) which also has a pulsed clock input terminal, and a full-keeper (734, 736) in the second stage, provides time borrowing capability and reduced sensitivity to clock jitter in high frequency designs. In an embodiment, both the evaluate of the first domino stage (718) of a block and the self-terminating precharge of the last domino stage (746) of the block are initiated by the rising edge of a pulsed clock (702). In a circuit configuration in accordance with the present invention, a time period approximately equivalent to three inverter delays is provided to turn off the inputs to a subsequent domino logic stage, thus providing adequate time to evaluate the first domino logic stage in each block.