Adjustment of transistor gate resistance in an integrated circuit involves exposing polysilicon of initial gate, forming gate extension by selective epitaxial deposition of a polysilicon layer, and siliciding the gate extension

摘要

Adjustment of gate resistance of a transistor produced in a semiconductor substrate and covered with an insulating layer comprises: exposing the polysilicon of the initial gate (G1) of transistor (T1) surrounded by spacers (E1); forming a gate extension (GX1) by selective epitaxial deposition of a polysilicon layer; and siliciding at least part of the gate extension (GX1), to form a final gate. Preferred Features: The gate extension (GX1) is made to project laterally with respect to the initial gate. The whole of the gate extension (GX1) is preferably silicided. The process can be applied to an integrated circuit having complementary transistors, where each stage of the process is carried out simultaneously for all the transistors of the integrated circuit. An independent claim is given for an integrated circuit comprising at least one transistor produced in a semiconductor substrate and containing a silicided gate, where the gate comprises a lower part (G1) surrounded by insolating spacers (E1), and a gate extension (GX1) located above the lower part (G1) and covered at least partially with a metal silicide layer (GXS1). Preferably, the gate extension (GX1) covered with the metal silicide layer (GXS1) is larger than the lower part (G1) of the gate.