System and method for propagating clock nodes in a netlist of circuit design

摘要

In accordance with one aspect of the invention, a method evaluates an element of the netlist, and ensures that a gate node of the element is defined as a clock node. Then, the method determines whether a first channel node of the element has already been designated as a clock node. If not, the method determines that the clock signal should be propagated through the element, and marks the first channel node as a clock node. Thereafter, the method evaluates another element that is gate connected to the first channel node, and repeats the above-listed steps on the another element. In accordance with another aspect of the invention, a method evaluates an element of the netlist, ensures that a gate node of the element is defined as a clock node, ensures that a channel node (either source or drain) of the element is not a precharge node, and ensures that the channel node of the element is not a predischarge node. In accordance with yet another aspect of the invention, the method evaluates a logic gate, wherein the gate node of the FET element is the input of the logic gate. In accordance with this aspect, the method determines an output node of the logic gate, ensures that the output node is not a precharge node, and ensures that the output node of the gate is not a predischarge node.