首页> 外国专利> Semiconductor integrated circuit device including circuit block having hierarchical structure and method of designing the same

Semiconductor integrated circuit device including circuit block having hierarchical structure and method of designing the same

机译:包括具有分层结构的电路块的半导体集成电路器件及其设计方法

摘要

A semiconductor integrated circuit device of low power consumption having a hierarchical structure is obtained. This semiconductor integrated circuit device employs at least one gated clock selected from a group including at least three gated clocks consisting of at least two gated clocks generated by employing at least two operation control signals output to different hierarchies as gate signals and a prescribed gated clock input in a circuit block of the most significant hierarchy as a gated clock input in circuit blocks of lower hierarchies below a third hierarchy among the plurality of circuit blocks. Thus, a plurality of gated clocks for reducing power consumption are readily mechanically decided. When at least one gated clock satisfying a prescribed circuit constraint is selected from the plurality of gated clocks, a semiconductor integrated circuit device of low power consumption is readily obtained.
机译:获得具有分级结构的低功耗的半导体集成电路器件。该半导体集成电路装置采用从包括至少三个选通时钟的组中选出的至少一个选通时钟,该选通时钟由至少两个选通时钟组成,该选通时钟是通过使用输出到不同层级的至少两个操作控制信号作为选通信号和规定的选通时钟输入而产生的。在最重要的层级的电路块中的“门控时钟”输入是在多个电路块中低于第三层级的较低层级的电路块中的门控时钟输入。因此,可以容易地机械地确定用于减少功耗的多个门控时钟。当从多个选通时钟中选择至少一个满足规定的电路约束的选通时钟时,容易获得低功耗的半导体集成电路器件。

著录项

  • 公开/公告号US2002070759A1

    专利类型

  • 公开/公告日2002-06-13

    原文格式PDF

  • 申请/专利权人 SANYO ELECTRIC CO. LTD.;

    申请/专利号US20010011978

  • 发明设计人 TATSUSHI OHYAMA;HIDEKI YAMAUCHI;

    申请日2001-12-11

  • 分类号H03K19/00;

  • 国家 US

  • 入库时间 2022-08-22 00:52:50

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