Semiconductor memory device having data parallel/serial conversion function and capable of efficiently performing operational test

摘要

A semiconductor memory device according to the present invention includes a memory core portion, a test mode control circuit for transmitting data output from the memory core portion to an internal node, and a data input/output control circuit for inputting/outputting in series a plurality of pieces of parallel data input/output to each internal node to a data node. The test mode control circuit transmits read data from the memory core portion as it is to the internal node in a normal reading operation, and compresses data output from the memory core portion on the basis of a prescribed unit and transmits the data to the internal node in a test mode. Therefore, the test data compressed for each prescribed unit can be input/output by using a smaller number of data nodes in the test mode than in the normal operation mode.