/ SEMICONDUCTOR MEMORY DEVICE HAVING DATA PARALLEL/SERIAL CONVERSION FUNCTION AND CAPABLE OF EFFICIENTLY PERFORMING OPERATIONAL TEST

摘要

The semiconductor memory device 110 according to the present invention includes a memory core unit 20, a test mode control circuit 200 for transferring data output from the memory core unit 20 to the internal nodes N0 to Nn. And a data input / output control circuit 40 for serially inputting and outputting a plurality of parallel data input and output to each of the internal nodes N0 to Nn at each of the data nodes Nd0 to Ndn. The test mode control circuit 200 transfers the read data from the memory core unit 20 as it is to the internal nodes N0 to Nn in the normal read operation, and outputs it from the memory core unit 20 in the test mode. Compressed data is applied to the data at predetermined units and transferred to the internal nodes N0 to Nn.;Therefore, in the test mode, the test mode compressed for each predetermined unit can be input and output using fewer test nodes than in the normal operation.