erfindungsgemu00e4u00df is to test a referenztaktsignal a first verzu00f6gerungsstrecke with a fixed delay, and a second verzu00f6gerungsstrecke with a variable delay is created, each with a receipt of the graphics circuit are connected to a data transmission the graphics circuit triggerwith the first clock signal and the second verzu00f6gerungsstrecke a verzu00f6gerungsstrecke a datensignal to getaktete arrives with the variable delay circuit, a range u0394tv n equidistant steps and a grundverzu00f6gerung u0394t in the range of [tf nu0394t / 2; tf + nu0394t / 2] in the fixed delay tf at least nu0394t / 2 respectively.to calibrate the range of the variable delay and fixed delay at the k times the value of the variable delay is increased gradually from n = 0 to is incremented until three phase change from being detected.where the value of n at the time of the first phasendurchgangs variable delay for the setup time and the value of n at the time of the third phasendurchgangs variable delay for the hold time.
展开▼
机译：erfindungsgem u00e4 u00df将测试具有固定延迟的第一个verz u00f6gerungsstrecke的参考信号，并创建具有可变延迟的第二个verz u00f6gerungsstrecke，每个带有图形电路的接收端都与数据传输相连通过第一个时钟信号和第二个时钟信号触发，然后通过可变延迟电路，等距步距范围和[tf n u0394]范围内的grundverz u0394tv到达要获取的日期信号。 / 2; tf + n u 2分别在固定延迟tf中至少n u0394t /2。以校准可变延迟和固定延迟的范围，在k倍处，可变延迟的值从n开始逐渐增加= 0到0一直增加到检测到三相变化为止。其中，第一阶段的n值在建立时间时为延迟，第三阶段的n值在保持时间之前为第三时变。
展开▼
