OUTPUT CIRCUIT, INPUT CIRCUIT, ELECTRONIC CIRCUIT, MULTIPLEXER, DEMULTIPLEXER, WIRED OR CIRCUIT, WIRED AND CIRCUIT, PULSE PROCESSING CIRCUIT, MULTI-PHASE CLOCK PROCESSING CIRCUIT, AND CLOCK MULTIPLICATION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To roughly match the propagation delay time of respective signal routes without using a low resistance process even when wiring lengths are different.;SOLUTION: Output nodes (a)-d are respectively provided on the output side of transmission gates TG2, TG4, TG6 and TG8 and the output nodes (a)-d are connected so as to equalize the wiring lengths. Also, the output nodes (a) and d at both ends are provided with inverters IV11 and IV12 and a common node e is provided on a position where the wiring lengths from the respective inverters IV11 and IV12 are equal.;COPYRIGHT: (C)2003,JPO