Output circuit, input circuit, electronic circuit, multiplexer, demultiplexer, wired-OR circuit, wired-AND circuit, pulse processing circuit, multi-phase clock processing circuit and a clock multiplier circuit

摘要

A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG 2 , TG 4 , TG 6 , and TG 8 , these output nodes a to d are connected so as to have an equal wiring length, inverters IV 11 and IV 12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV 11 and IV 12 becomes identical.