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Method for assigning power and ground pins in array packages to enhance next level routing

机译:在阵列封装中分配电源和接地引脚以增强下一级布线的方法

摘要

A method for assigning power and ground pins in array packages in order to enhance next level routing is provided. In one embodiment, the method comprises arranging connections of a semiconductor array package, the semiconductor package having an integrated circuit with power, ground, and signal connections, in 23 connection grids. Each connection grid includes a power connection and a ground connection which is adjacent to the power connection. The 23 connection grids are arranged so that each connection at the periphery is a signal connection. A 4:1:1 signal:power:ground connection ratio is maintained in the arrangement, wherein no more than four signal connections are present for each power connection, and no more than four signal connections are present for each ground connection.
机译:提供了一种在阵列封装中分配电源和接地引脚以增强下一级布线的方法。在一个实施例中,该方法包括在23个连接网格中布置半导体阵列封装的连接,该半导体封装具有具有电源,接地和信号连接的集成电路。每个连接网格包括电源连接和与电源连接相邻的接地连接。排列23个连接网格,以便外围的每个连接都是信号连接。在该装置中保持4:1:1的信号:功率:接地连接率,其中每个电源连接不超过四个信号连接,并且每个接地连接不超过四个信号连接。

著录项

  • 公开/公告号US6521846B1

    专利类型

  • 公开/公告日2003-02-18

    原文格式PDF

  • 申请/专利权人 SUN MICROSYSTEMS INC.;

    申请/专利号US20020041019

  • 发明设计人 MICHAEL C. FREDA;PRABHANSU CHAKRABARTI;

    申请日2002-01-07

  • 分类号H05K11/60;

  • 国家 US

  • 入库时间 2022-08-22 00:05:58

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