Short-circuit failure analyzing method and apparatus

摘要

A setting of a logical state in an integrated circuit is changed, a plurality of measurement patterns which are used in a quiescent power source current test of the integrated circuit are formed, an internal state value 0/1 of each net at the time when the measurement patterns are supplied by a simulation of the integrated circuit is derived, and further, a pass or fail test result is obtained every measurement pattern by the quiescent power source current test in which a plurality of measurement patterns were supplied to the integrated circuit determined to be a defective device. A state value variable in which the internal state values of all measurement patterns have been stored every net and a test result variable in which the pass or fail test result has been stored every measurement pattern are formed on the basis of those measurement patterns, internal state values, and test results. A combination of the state value variable of each net and the test result variable are compared between the nets, thereby discriminating a short-circuit failure position in the integrated circuit.