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Method of forming CMOS transistor having a deep sub-micron mid-gap metal gate

机译:具有深亚微米中间隙金属栅的CMOS晶体管的形成方法

摘要

A CMOS transistor is formed on a single crystal silicon substrate. Active regions are formed on the substrate, including an nMOST active region and a pMOST active region. An epitaxial layer of undoped silicon is formed over the active regions. Out-diffusion from the underlying active regions produces dopant densities within the epitaxial layer one, or more, orders of magnitude lower than dopant densities within the underlying active regions. In a preferred embodiment, the epitaxial layer is counter doped by implanting ions of the opposite type to those within the underlying active region. Counter doping further reduces the dopant density, to reduce the threshold voltage further.
机译:在单晶硅衬底上形成CMOS晶体管。有源区域形成在基板上,包括nMOST有源区域和pMOST有源区域。在有源区上方形成未掺杂硅的外延层。来自下面的有源区的外扩散在外延层内产生的掺杂剂密度比下面的有源区内的掺杂剂密度低一个或多个数量级。在一个优选的实施方案中,通过注入与下面的有源区域内的离子相反类型的离子,对外延层进行反掺杂。反向掺杂进一步降低了掺杂剂密度,从而进一步降低了阈值电压。

著录项

  • 公开/公告号US6613626B1

    专利类型

  • 公开/公告日2003-09-02

    原文格式PDF

  • 申请/专利权人 SHARP LABORATORIES OF AMERICA INC.;

    申请/专利号US20000604136

  • 发明设计人 SHENG TENG HSU;

    申请日2000-06-27

  • 分类号H01L218/234;H01L212/00;H01L213/60;H01L212/20;H01L213/80;

  • 国家 US

  • 入库时间 2022-08-22 00:05:26

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