Method of forming deep sub-micron CMOS transistors with self- aligned silicided contact and extended S/D junction

摘要

The present invention includes forming an oxide layer on a substrate. An undoped polysilicon layers is deposited by chemical vapor deposition on the gate oxide layer. Next, a silicon nitride layer is successively formed on the polysilicon layer to act as an anti- reflective coating (ARC). Then, the undoped polysilicon layer, ARC layer, and the oxide layer are patterned to form ultra short channel polysilicon gates. A thermal annealing is performed to recover the etching damage in the substrate and generate a pad oxide layer on the surface of the polysilicon gate and the substrate. An nitrogen-doped amorphous silicon layer is formed on the gate structure and on the pad oxide. Next, an ion implantation is carried out to dope dopants into the gate and substrate, thereby forming source and drain. A steam oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped thermal silicon dioxide layer. Simultaneously, an ultra- shallow extended source and drain junction adjacent to the gate structure is obtained by using the amorphous silicon layer as a diffusion source. Subsequently, the nitrogen-doped silicon dioxide layer is etched back to form oxide spacers. Then, the cap silicon nitride layer are removed. Then, two-step silicidation process are used to form silicided contacts.