SEMICONDUCTOR DEVICE INCLUDING TESTER CIRCUIT SUPPRESSIBLE OF CIRCUIT SCALE INCREASE AND TESTING DEVICE OF SEMICONDUCTOR DEVICE

摘要

After writing data into a memory cell array according to an internal address signal, data read out from each memory cell is compared with expected value data in a read out operation. When there are two spare rows and two spare columns provided, a replacement determination unit (3100.1-3100.6) is provided for each of the sixth types of sequences sequentially replacing a memory cell row and a memory cell column. A defective address is written into four sets of storage cell trains provided corresponding to each replacement determination unit (3100.1-3100.6) only when a defective memory cell is detected having an address differing from at least one of a row address and column address of a defective memory cell that is already stored. IMAGE