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integrated circuit comprising a circuit for scrambling clinical recorded in a volatile memory zone.

机译:集成电路,包括用于扰乱记录在易失性存储区中的临床的电路。

摘要

The invention relates to an integrated circuit (mp2) comprising a volatile memory zone (dtmem), the content of which has a value determined after a reset to zero of the integrated circuit, the volatile memory zone being connected to a data bus dtb) (by means of a scrambler circuit (jmct) ensuring the coding of the data recorded in the memory zone and the decoding of the data read in the memory zone, the coding of the data being at least a function of a key (ks) applied to the scrambler circuit. According to the invention, the wrench applied to the scrambler circuit is a random key delivered by a generator of a random signal (rgen) arranged in order to change the value of the key at least at each new resetting to zero of the integrated circuit.
机译:本发明涉及一种包括易失性存储区(dtmem)的集成电路(mp2),其内容具有在将集成电路复位为零之后确定的值,该易失性存储区连接至数据总线dtb)(通过加扰器电路(jmct)来确保对存储区中记录的数据进行编码,并对存储区中读取的数据进行解码,该数据的编码至少是施加于存储区的密钥(ks)的函数根据本发明,加扰器电路上使用的扳手是由随机信号发生器(rgen)传递的随机密钥,该随机信号的产生是为了至少在每次新的重置为零时改变密钥的值。集成电路。

著录项

  • 公开/公告号FR2818845B1

    专利类型

  • 公开/公告日2003-03-21

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS SA;

    申请/专利号FR20000016747

  • 发明设计人 WUIDART SYLVIE;

    申请日2000-12-21

  • 分类号H04L9/18;G06F12/14;

  • 国家 FR

  • 入库时间 2022-08-21 23:38:05

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