Semiconductor memory device row decoder structures having reduced layout area, and methods of operating the same

摘要

Semiconductor memory device row decoder structures have reduced layout area. A structure for erasing memory cells coupled to a single bitline includes a single bias driver for these cells, and a plurality of local voltage level converters coupled to the bias driver. At least one word line driver is coupled to each local level converter, to erase at least one of the memory cells. A global word line is also coupled to the word line driver. A method for erasing these memory cells includes biasing the local level converter, for powering in turn a component of the word line driver. In addition, an existing global word line driver powers another component of the word line driver, thus resulting in reduced design requirements for the local level converter.