The invention concerns an inductance formed in metal layers (Mn, Vn, Mn+1) of an integrated circuit and wound in a plane parallel to a main surface of the integrated circuit. The invention is characterised in that each winding of the inductance comprises in a plane perpendicular to the integrated circuit main surface: in a first metal layer (Mn), parallel lower conductive lines (211, 212, 213) extending along the inductance pattern; in a second metal layer (Vn), feedthroughs (231, 232, 233, 234, 235, 236), each subjacent conductive line being associated with at least two feedthroughs; and in a third metal layer (Mn+1), upper conductive lines (251, 252, 253, 254) interconnected to the subjacent conductive lines via the feedthroughs, the lower and upper conductive lines being offset relative to one another so as to ensure electrical continuity.
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