8.4 Fully Integrated Buck Converter with 78 Efficiency at 365mW Output Power Enabled by Switched-Inductor Capacitor Topology and Inductor Current Reduction Technique

摘要

Fully integrated buck converters can improve performance and reduce the power consumption of system-on-chip by providing point-of-load regulation with dynamic voltage scaling [1]. As a core component of a buck converter, an inductor with large inductance and small resistance is desirable for high power efficiency, but on-chip inductor integration is challenging due to silicon-area constraints and parasitic effects. Common techniques to integrate on-chip inductors include using on-die spiral inductors [1-3], package bond wires [4], and magnetic cores [5,6], resulting in inductors on the order of nH with resistances of several hundred m μ. Switching frequencies approaching 100MHz and beyond are often used to reduce the current ripple of such small inductors [1-6] at the cost of switching loss. A special hybrid topology, known as a 3-level converter, has been shown to reduce inductor current ripple and the associated power loss by doubling the effective switching frequency [1]. Compared to the conventional buck converter, the 3level topology uses two more power switches that contribute toward switching loss and conduction loss. Some other hybrid topologies have demonstrated unique characteristics and benefits [7], but none have been proposed to improve the performance of fully integrated buck converters.