process for the fabrication of mosfets with improved short channel effects

摘要

In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1 x 1013/cm2 to 5 x 1016/cm2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants. IMAGE