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Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor

机译:减少应变层场效应晶体管中位错引起的泄漏的方法

摘要

A structure and method of fabricating a semiconductor field-effect transistor (MOSFET) such as a strained Si n-MOSFET where dislocation or crystal defects spanning from source to drain is partially occupied by heavy p-type dopants. Preferably, the strained-layer n-MOSFET includes a Si, SiGe or SiGeC multi-layer structure having, in the region between source and drain, impurity atoms that preferentially occupy the dislocation sites so as to prevent shorting of source and drain via dopant diffusion along the dislocation. Advantageously, devices formed as a result of the invention are immune to dislocation-related failures, and therefore are more robust to processing and material variations. The invention thus relaxes the requirement for reducing the threading dislocation density in SiGe buffers, since the devices will be operable despite the presence of a finite number of dislocations.
机译:诸如应变Si n-MOSFET之类的半导体场效应晶体管(MOSFET)的结构和制造方法,其中位错或从源极到漏极的晶体缺陷部分被重的p型掺杂剂占据。优选地,所述应变层n-MOSFET包括Si,SiGe或SiGeC多层结构,所述Si,SiGe或SiGeC多层结构在源极和漏极之间的区域中具有优先占据所述位错位点的杂质原子,从而防止了由于掺杂剂扩散引起的源极和漏极的短路。沿着错位。有利地,作为本发明的结果而形成的装置不受与位错相关的故障的影响,因此对于处理和材料变化更坚固。因此,本发明放松了降低SiGe缓冲器中的螺纹位错密度的要求,因为尽管存在有限数量的位错,但这些装置仍可操作。

著录项

  • 公开/公告号US2005104092A1

    专利类型

  • 公开/公告日2005-05-19

    原文格式PDF

  • 申请/专利权人 STEVEN J. KOESTER;

    申请/专利号US20030717279

  • 发明设计人 STEVEN J. KOESTER;

    申请日2003-11-19

  • 分类号H01L29/76;H01L21/335;

  • 国家 US

  • 入库时间 2022-08-21 22:26:00

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