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Process for making a gate for a short channel CMOS transistor structure

机译:制造用于短沟道CMOS晶体管结构的栅极的工艺

摘要

The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps:;a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching,;b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material,;c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.
机译:用于制造CMOS晶体管结构的栅极的方法技术领域本发明涉及一种用于制造CMOS晶体管结构的栅极的方法,该CMOS晶体管的结构由在衬底的半导体材料中的面上实现的堆叠构成,所述堆叠包括栅极隔离层,栅极材料层和栅极掩模。依次地,该工艺包括以下步骤:a)各向异性蚀刻未被栅极掩模掩盖的栅极材料层的顶部,该蚀刻步骤留下栅极材料层的底部并导致形成由各向异性刻蚀产生的刻蚀面上的刻蚀产物组成的沉积物; b)处理刻蚀产物组成的沉积物,以增强保护层,以防随后对栅极材料进行刻蚀; c)刻蚀底部的刻蚀栅极材料层直至栅极隔离层,该蚀刻包括对栅极材料层的各向同性蚀刻,以使栅极在底部比在顶部短。

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