首页> 外国专利> STRUCTURE OF CMOS TRANSISTOR FOR PREVENTING SHORT CHANNEL EFFECT BY ADJUSTING LENGTH OF CHANNEL AND FABRICATING METHOD THEREOF

STRUCTURE OF CMOS TRANSISTOR FOR PREVENTING SHORT CHANNEL EFFECT BY ADJUSTING LENGTH OF CHANNEL AND FABRICATING METHOD THEREOF

机译:调整通道长度防止短通道效应的CMOS晶体管结构及其制造方法

摘要

PURPOSE: A structure of a CMOS transistor and a fabricating method thereof are provided to prevent a short channel effect by adjusting a length of a channel according to a depth of a trench. CONSTITUTION: First and second conductive wells(114,116) are formed within a semiconductor substrate having a trench etched from a surface thereof. A well division layer(112a) is formed under a trench bottom between the first and the second conductive wells. A second conductive junction layer is formed vertically to the trench bottom and a surface of the first conductive well. A first conductive junction layer is formed vertically to the trench bottom and a surface of the second conductive well. A gate electrode(124) is formed by burying an insulating layer into the trench of the first and the second conductive wells.
机译:目的:提供一种CMOS晶体管的结构及其制造方法,以通过根据沟槽的深度调节沟道的长度来防止短沟道效应。构成:第一和第二导电阱(114,116)形成在具有从其表面蚀刻出的沟槽的半导体衬底内。在第一和第二导电阱之间的沟槽底部下方形成阱划分层(112a)。垂直于沟槽底部和第一导电阱的表面形成第二导电结层。第一导电结层垂直于沟槽底部和第二导电阱的表面形成。通过将绝缘层掩埋到第一和第二导电阱的沟槽中来形成栅电极(124)。

著录项

  • 公开/公告号KR20050007782A

    专利类型

  • 公开/公告日2005-01-21

    原文格式PDF

  • 申请/专利权人 MAGNACHIP SEMICONDUCTOR LTD.;

    申请/专利号KR20030047382

  • 发明设计人 KIM SUNG JIN;

    申请日2003-07-11

  • 分类号H01L27/092;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:59

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