A clock signal generator (128) for generating N sub-sampling clock signals from a master clock signal, and an analog sampling circuit (140) and analog-to-digital convener (100) incorporating same. Each of the sub-sampling dock signals generated by the clock signal generator has fast and precisely-timed edges. The clock signal generator comprises a clock window signal generating circuit (149) and N gate circuits (e.g., 151), where N is an integer greater than unity. The clock window signal generating circuit is connected to receive the master dock signal and derives N dock window signals having imprecisely-timed edges from the master clock signal. Each of the N gate circuits generates one of the sub-sampling clock signals with logic states defined by one of the clock window signals and with edge timings defined by the master clock signal independently of the imprecisely-timed edges of the clock window signal, and includes a first input (e.g., 159), a second input (e.g., 167) and an output (169). The first input is connected to receive the clock window signal, the second input is connected to receive the master clock signal, and the output provides the sub-sampling clock signal.
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机译：时钟信号发生器（128），用于从主时钟信号产生 N 个子采样时钟信号;以及模拟采样电路（140）和包含该采样信号的模数转换器（100）。时钟信号发生器产生的每个子采样对接信号具有快速且精确定时的边沿。时钟信号产生器包括时钟窗口信号产生电路（149）和 N 个门电路（例如151），其中 N 是大于1的整数。时钟窗口信号发生电路被连接以接收主坞信号，并从主时钟信号中得出具有不精确定时的边沿的 N 个坞窗口信号。 N 个门电路中的每一个都生成一个子采样时钟信号之一，该子采样时钟信号具有由时钟窗口信号之一定义的逻辑状态，并且具有由主时钟信号定义的边沿时序，与不精确计时的边沿无关时钟窗口信号的“时钟”信号，并包括第一输入（例如159），第二输入（例如167）和输出（169）。连接第一输入以接收时钟窗口信号，连接第二输入以接收主时钟信号，而输出提供子采样时钟信号。
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