Parallel analog sampling circuit and analog-to-digital converter system incorporating clock signal generator generating sub-sampling clock signals with fast and precisely-timed edges

摘要

The analog sampling circuit samples an analog input signal at intervals of time precisely defined by a master clock signal. The analog sampling circuit comprises N track-and-hold circuits and a clock signal generator. Each of the track-and-hold circuits includes a clock signal input. The clock signal generator includes a clock window signal generator and N gate circuits. The clock window signal generator comprises an input connected to receive the master clock signal, and N outputs, derives clock window signals from the master clock signal and feeds one of the clock window signals to each of the outputs. The clock window signals have imprecisely-timed edges. Each of the N gate circuits generates a sub-sampling clock signal with logic states defined by one of the clock window signals and with edge timings defined by the master clock signal independently of the imprecisely-timed edges of the clock window signal, and comprises a first input, a second input and an output. The first input is connected to one of the outputs of the clock window signal generator, the second input is connected to receive the master clock signal and the output is connected to the clock signal input of one of the track-and-hold circuits. The N-channel analog-to-digital conversion system includes the analog sampling circuit just described and an analog-to-digital converter connected to the analog output of the each of the N track-and-hold circuits.