首页> 外国专利> NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING MOS TRANSISTOR HAVING FLOATING GATE AND CONTROL GATE TO SIMPLIFY SEMICONDUCTOR FABRICATION PROCESS

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING MOS TRANSISTOR HAVING FLOATING GATE AND CONTROL GATE TO SIMPLIFY SEMICONDUCTOR FABRICATION PROCESS

机译:非易失性半导体存储器件,包括具有浮栅和控制栅的MOS晶体管,可简化半导体制造过程

摘要

PURPOSE: A non-volatile semiconductor memory device including a MOS transistor having a floating gate and a control gate to simplify a semiconductor fabrication process is provided to simplify the fabrication process of the non-volatile semiconductor memory device by simplifying a reliability inspection for a memory cell and a reliability inspection for a capacitor within a boosting circuit. CONSTITUTION: A memory cell includes the first MOS transistor having a charge accumulation layer and a control gate formed on the charge accumulation layer having an inter-gate insulating layer. A boosting circuit(17,18) is used for generating a voltage supplied to the memory cell. The boosting circuit includes a capacitor element. The capacitor element includes first and second semiconductor layers, a capacitor insulating layer, and the third semiconductor layer. The first and second semiconductor layers are formed on a semiconductor substrate. The capacitor insulating layer is formed on a top part and a lateral part of each of the first and second semiconductor layers and on the semiconductor substrate between the first and second semiconductor layers. The capacitor insulating layer is formed with the same material as the inter-gate insulating layer. The third semiconductor layer is formed on the capacitor insulating layer, is connected electrically to the first semiconductor layer, and is isolated electrically from the second semiconductor layer.
机译:目的:提供一种包括具有浮置栅极和控制栅极的MOS晶体管以简化半导体制造工艺的非易失性半导体存储器件,以通过简化存储器的可靠性检查来简化非易失性半导体存储器件的制造工艺电池和升压电路中电容器的可靠性检查。构成:一个存储单元包括具有电荷积累层的第一MOS晶体管和形成在具有栅间绝缘层的电荷积累层上的控制栅。升压电路(17,18)用于产生提供给存储单元的电压。升压电路包括电容器元件。电容器元件包括第一和第二半导体层,电容器绝缘层和第三半导体层。第一和第二半导体层形成在半导体衬底上。电容器绝缘层形成在第一半导体层和第二半导体层的每个的顶部和侧面上以及第一半导体层和第二半导体层之间的半导体基板上。电容器绝缘层由与栅间绝缘层相同的材料形成。第三半导体层形成在电容器绝缘层上,电连接至第一半导体层,并且与第二半导体层电隔离。

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