首页> 外国专利> METHOD FOR FORMING BUMP OF METAL LINE IN SEMICONDUCTOR FOR IMPROVING ELECTRICAL PROPERTIES OF SEMICONDUCTOR BY PREVENTING MISALIGNMENT OF BUMP DUE TO STEP OF PASSIVATION LAYER

METHOD FOR FORMING BUMP OF METAL LINE IN SEMICONDUCTOR FOR IMPROVING ELECTRICAL PROPERTIES OF SEMICONDUCTOR BY PREVENTING MISALIGNMENT OF BUMP DUE TO STEP OF PASSIVATION LAYER

机译:在半导体中形成金属线凹凸的方法,通过钝化层的步骤防止凹凸不平,从而改善半导体的电性能

摘要

PURPOSE: A method for forming a bump of a metal line in a semiconductor is provided to improve electrical properties of the semiconductor by preventing misalignment of a bump due to a step of a passivation layer. CONSTITUTION: A metal line(104) is formed on a semiconductor chip(102). A thick oxide layer(106) is formed on the entire surface of the semiconductor chip. The oxide layer is planarized. A silicon nitride layer(108) is formed on the oxide layer. A passivation layer for partially exposing an upper part of the metal line is formed thereon by removing selectively the silicon nitride layer and the oxide layer. A bump(112) is formed on the metal line by using a screen printing method.
机译:目的:提供一种用于在半导体中形成金属线的凸块的方法,以通过防止由于钝化层的台阶而引起的凸块的未对准来改善半导体的电性能。组成:一条金属线(104)形成在半导体芯片(102)上。在半导体芯片的整个表面上形成厚的氧化物层(106)。氧化层被平坦化。在氧化物层上形成氮化硅层(108)。通过选择性地去除氮化硅层和氧化物层,在其上形成用于部分暴露金属线的上部的钝化层。通过使用丝网印刷方法在金属线上形成凸块(112)。

著录项

  • 公开/公告号KR20050004408A

    专利类型

  • 公开/公告日2005-01-12

    原文格式PDF

  • 申请/专利权人 DONGBUANAM SEMICONDUCTOR INC.;

    申请/专利号KR20030044576

  • 发明设计人 KIM YEONG SIL;

    申请日2003-07-02

  • 分类号H01L21/60;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:02

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号