Pau of the semiconductor memory device Wars down control circuit

摘要

PURPOSE: A control circuit of power down for semiconductor memory device is provided to perform an entering and a removing operations of a power down mode in an LVTTL level or an SSTL level of an inputting signal. CONSTITUTION: A power down mode is entered when a CKE(Control Pin of Clock) becomes from a logical 'high' to a logical 'low' as a VIL(High Voltage Level) level. An output PCKE(Buffered Clock Control Pin) of a differential amplification typed inputting buffer(10) becomes the logical 'low'. A CKBPU(Output Signal of an OR Circuit) becomes the logical 'low' and a POFF(Entering Signal of Power Down Mode) becomes the logical 'high'. The differential amplification typed inputting buffer(10) is tuned off and a latch typed input buffer(12a) of a power down removing circuit(12) is turned on. And every general input buffers are turned on. That is to be the power down mode. In becoming the CKE from the logical 'low' to the logical 'high' as a VIH level, a PSELFX as a removing signal of power down mode becomes the logical 'high' by the latch typed input buffer(12a). The CKEBPU becomes the logical 'high' and the POFF as an entering signal of power down mode becomes the logical 'low'. Thereby, the differential amplification typed inputting buffer(10) is tuned on and the latch typed input buffer(12a) is turned off. And every general input buffers are turned off.