Integrated circuit memory device e.g. fast cycle dynamic RAM, for use in e.g. consumer application, has write data path with N data lines connecting N switches to memory cell array to write N data bits in parallel

摘要

The device (400) has a memory cell array (410) with a group of memory cells. A write data path (420) serially receives 2N data bits from an external terminal. The data path has 2N write data buffers (422) that are configured to store the 2N data bits from the write data path, and 2N switches (424). N data lines (412) connect N of the 2N switches to the memory cell array to write N data bits in parallel. An independent claim is also included for a method of operating an integrated circuit device.