In a CCD driving circuit, it is difficult to reduce the consumption power while maintaining the charge transfer performance. In this connection, when BUFk switches an output φka to a clock signal line, firstly, a clock signal line 10−k is set to a floating state, charge/discharge between the clock signal line 10−k and a capacitor C is carried out. For instance, electric charges of a clock signal line 10−1 of which φ1 is Vp are partially charged to the capacitor C. Before Vp is applied to the clock signal line 10−2 from BUF2, a potential φ2 is raised to a potential between Vp and 0 when the capacitor C charges the clock signal line 10−2. When the BUF2 supplies a current corresponding to a portion of a remaining voltage to the clock signal line 10−2, φ2 can be raised to Vp.
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机译：在CCD驱动电路中，难以在维持电荷转移性能的同时降低消耗功率。关于这一点，当BUFk将输出φ ka 切换到时钟信号线时，首先，将时钟信号线 10 -k 设置为在浮动状态下，在时钟信号线 10 -k 和电容器C之间进行充电/放电。例如，时钟信号线 10 −1 的电荷部分为φ 1 为V p V p 从BUF 2 施加到时钟信号线 10 -2 之前被充电到电容器C。 ，当电容器C对时钟信号线 10 -充电时，电势φ 2 上升到V p 和0之间的电势。 2 。当BUF 2 向时钟信号线 10 -2 提供对应于一部分剩余电压的电流时，φ 2 可以提高到V p 。
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