首页> 外国专利> Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines

Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines

机译:导电线,形成导电线的方法以及减少在多晶硅晶体管栅极线上制造硅化钛的过程中的硅化钛结块的方法

摘要

The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0. The silicon-comprising layer, the electrically conductive layer, the MSixNy-comprising layer, the MSiz-comprising layer, and the TiSia-comprising layer are patterned into a stack comprising an electrically conductive line. Other aspects and implementations are contemplated.
机译:本发明包括导电线,形成导电线的方法以及减少在多晶硅晶体管栅极线上的硅化钛的制造中的硅化钛聚结的方法。在一个实施方案中,一种形成导电线的方法包括在衬底上方提供含硅层。在含硅层上方形成导电层。在导电层上形成包含MSi x N y 的层,其中“ x”为0至3.0,“ y”为0.5至10,并且“ M”是Ta,Hf,Mo和W中的至少一个。在MSi x N y上形成包含MSi z 的层 z 的层上形成包含TiSi a 的层,其中“ a”为1至3.0。含硅层,导电层,包含MSi x N y 的层,包含MSi z 的层以及将包含TiSi a 的层构图成包括导电线的堆叠。可以预期其他方面和实施方式。

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