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system and device for bussteuerung

机译:总线系统和设备

摘要

There is disclosed a bus control device which reduces the data traffic amount of a parallel bus to enhance the performance of the bus control device. A local CPU (111) controls a serial bus transmission/reception controller (113) to give a transmission timing to a transmission interface (120). The bus transmission/reception controller (113) transmits to a serial bus a transmission frame formed by reading predetermined transmission data from a memory (112) storing addresses of a plurality of units (4) connected to the serial bus (51) and transmission/reception data to be transferred to the plurality of units. As a result, transmission/reception is performed with units connected to the serial bus (51) out of the plurality of units via the serial bus, the destination address and transmission data are read from the memory during transmission, and reception data is written to the memory during reception. IMAGE
机译:公开了一种总线控制设备,该总线控制设备减少了并行总线的数据通信量以增强总线控制设备的性能。本地CPU(111)控制串行总线发送/接收控制器(113)以将发送定时提供给发送接口(120)。总线发送/接收控制器(113)向串行总线发送通过从存储器(112)读取预定的发送数据而形成的发送帧,该存储器(112)存储连接到串行总线(51)的多个单元(4)的地址并发送/接收数据被传送到多个单元。结果,利用经由串行总线连接到多个单元中的与串行总线(51)相连的单元进行发送/接收,在发送期间从存储器读取目的地地址和发送数据,并将接收数据写入接收期间的内存。 <图像>

著录项

  • 公开/公告号DE69736680D1

    专利类型

  • 公开/公告日2006-10-26

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI K.K.;

    申请/专利号DE19976036680T

  • 发明设计人 MITO;

    申请日1997-02-07

  • 分类号G06F13/36;G05B19/042;G05B19/414;G05B19/418;

  • 国家 DE

  • 入库时间 2022-08-21 21:18:04

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