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Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same
Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same
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机译:具有分裂栅读取晶体管和分裂栅编程晶体管存储单元的浮栅存储器及其制造方法
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摘要
Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
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