Memory cell programming or erasing method for electrically EPROM, involves applying non-zero compensation voltage to gate of MOS transistor, and applying inhibiting voltage to gate or source of floating gate transistor

摘要

The method involves simultaneously applying a high programming or erasing voltage (Vpp2) to a memory cell before being programmed or erased and to a terminal of a MOS transistor that is not involved in programming or erasing process. A non-zero compensation voltage (Vc) is applied to a gate of the transistor that is not involved in the programming or erasing process. An inhibiting voltage (hashVc) is applied to a gate or a source of a floating gate transistor that is connected to the MOS transistor.